A typical X86 family of processors communicates with off-chip memory and peripheral units such as a hard disk, keyboard, etc. through memory or I/O bus cycles. A memory bus cycle is used to fetch instructions and data from the system's memory or to write data to the system's memory. The memory may be on the system board, in ROM or RAM. The processor executes a memory instruction in response to, inter alia, a "mov" or "str" instruction. To execute a memory cycle, the processor asserts an M/IO# pin to a "1" and generates an address on address pins A31 through A3.
The I/O bus cycle is used to communicate with peripheral devices in the system such as a hard disk, keyboard, etc. An I/O cycle is initiated by the processor when it executes, inter alia, an IN instruction or an OUT instruction. To execute an I/O bus cycle, the processor sets the M/IO# pin to a "0" and generates an address on the address pins A3-A15. Each peripheral which communicates with the processor via an I/O bus cycle is assigned a portion of the 64 Kbytes address space provided by the address pins. The peripheral devices sense the address and determine when the address corresponds to its assigned address. A system bus controller attached to the system bus returns a READY signal to the processor in response to the initiation of a bus cycle when the address is latched.
In the prior art, the READY signal is used to create wait-states on the bus during an I/O bus cycle. For example, in the 8088 processor if the READY signal is held low until the rising edge of the next bus clock during an I/O bus cycle, a wait state is inserted. Thus, an I/O bus cycle of four clocks can be extended to five clocks. The READY signal can generate up to five wait states in any one I/O bus cycle. When the READY signal is again active, the I/O bus cycle ends. The bus cycle is normally four clocks in length or 1 microsecond for 4.77 MHz clock speed board designs, plus any additional wait states, for prior art systems.
When a system bus controller has control of the system bus, its timing signals are derived from the same clock signal that the processor uses. At higher processor speeds, the clock signal is doubled or tripled to produce the processor speed. All external parameters however are defined with respect to the clock signal's rising edge
With the advent of super-scalar, super-pipelined processors, processors are running at increasing speeds of 100 Mhz and more. At higher processor speeds, the system clock signal is doubled or tripled to produce the processor speed. This increasing speed of instructions by processors creates problems when executing I/O bus cycles. For example, a processor may execute an OUT instruction in a first clock and a second OUT instruction in the second clock. However, a peripheral is not able to respond to I/O write instructions in quick succession even when wait states are inserted in the bus cycle. Thus, when two OUT instructions specifying the same peripheral occur in quick succession, the peripheral may be unable to accept the data at the rate the data is transmitted. The peripheral is thus overrun because it can not accept the second I/O bus cycle. Peripheral overrun may result in loss of data or system slowdown because the data must be resent. This time from a first I/O write cycle to a second I/O write cycle for an I/O device to capture the data correctly is known as the I/O recovery time.
In the prior art, several suggestions to provide adequate I/O recovery time have been made. First, if back to back OUT instructions occur in a processor, the prior art suggests inserting a jump to the next instruction. The jump requires the processor to perform the next instruction before performing the second I/O instruction and place the second OUT instruction in memory. The second OUT instruction must then be fetched from memory again. This delay imposed by the memory read to fetch the second OUT instruction acts as a recovery period between back to back OUT instructions. However, this prior art solution will not work with some x86 type processors, such as the 486, because the OUT instruction may be stored on the on-chip cache when a jump occurs. The time to fetch the OUT instruction from an on-chip cache is only one processor clock cycle and is usually not an adequate period of time for I/O recovery.
Another suggestion in the prior art is to explicitly generate a read cycle to a non-cacheable location in memory. This would guarantee that a read bus cycle is performed between the back to back OUT instructions. The time that elapses during the non-cacheable memory read bus cycle will give the I/O device time to recover before the next I/O write bus cycle begins on the external buses. However, the location of a non-cacheable memory and cacheable memory is a configuration specific to each system platform. Thus, a program using this solution may fail in some system configurations.
A third solution suggested in the prior art has been to perform a "dummy" I/O read from an I/O location that will not be affected by the read operation. This dummy I/O read placed in between the back to back I/O write cycles guarantees at least two processor clock cycles of delay between the two I/O write cycles. This dummy I/O read however still requires an interruption in the order of processor instructions. Further, all three prior art suggestions fail if the I/O recovery period required is longer than the time necessary to perform the inserted instruction. Thus, for instance, if the I/O recovery time is longer than the period to perform the "dummy" I/O read, than peripheral overrun may still occur.
It is thus an object of the present invention to provide an apparatus and method of operating the same in which successive I/O bus cycles occur without peripheral overrun.
It is a further object of the present invention to provide an apparatus and method of operating the same in which the I/O bus cycles are performed with little interference in bus traffic.
It is still a further object of the present invention to provide an apparatus and method of operating the same in which the processor instruction order is not disturbed when providing I/O recovery time.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification.